Hierarchical Design Planning

Objective: Create design library using verilog for all blocks, create chip-level floorplan and dividing into subblocks by exploring physical design hierarchy to minimize runtime and increase parallelism for implementation.

Steps involved:

a. Link flat design

b. Explore hierarchies which can be converted to blocks

c. Committing hierarchies as blocks

d. Shaping Blocks and Voltage area

e. Macro placement for blocks

f. Power network for blocks and top

g. Global routing and pin creation

h. Interface Optimization/Timing estimation

i. Budgeting

j. Block/Top P&R